Over the recent years, Central Processing Units (CPUs) of computers have encountered a slowdown of improving performance through micronization. Consequently, it is examined that the high performance of the computer is attained by using circuit blocks of an Field Programmable Gate Array (FPGA) and other equivalent programmable logic devices as an accelerator of the CPU.
FIG. 1 illustrates a configuration of a computer 810 including the FPGA. The computer 810 is also called an information processing apparatus. The computer 810 in FIG. 1 includes a CPU 801, a memory 802 and an FPGA 805. The CPU 801 and the FPGA 805 are interconnected via an expansion bus 804A. The FPGA 805 includes a control unit/bus bridge 852, and communicates with the CPU 801 via the expansion bus 804A. The FPGA 805 includes a plurality of User Defined Logics (UDLs) 851. Each UDL 851 communicates with the CPU 801 and the memory 802 via the control unit/bus bridge 852 and the expansion bus 804A.
The CPU 801 provides a plurality of Virtual Machines (VMs) 812. The VMs 812 are also called virtual computers. The virtual computer provides a user with a virtual CPU as a resource. The CPU 801 of the computer 810 providing these virtual machines is also called a physical CPU. The memory 802 is also called a physical memory. The CPU 801 includes a cache 811 in an example of FIG. 1.
The recent computers have a spread of virtual computer technologies, in which a larger number of virtual CPUs than a number of physical CPUs are usable in the example of FIG. 1. In other words, the users use virtual computing resources via a network on the virtual computers, without having physical computing resources. The users can increase or decrease the computing resources according to necessity without purchasing the physical computing resources instanced by the physical CPUs and the physical memories, while the virtual computers provide cloud services. On the other hand, a device, e.g., the FPGA including the circuit block serving as the accelerator of the physical CPU or the virtual CPU comes to be installed with a partially rewritable function of the circuit while operating the circuit.
By the way, when the accelerators frequently using the bus operate simultaneously, a bus conflict occurs and affects performance of a whole system as the case may be. Particularly when the respective accelerators are universally designed, such a problem arises as to consume bus bandwidths equal to or larger than the bandwidths satisfying a request of a requester (user) of the accelerators. Such being the case, the prior arts involve performing proper arbitration or allocation of the bandwidths on the premise that properties of the accelerators are previously known to some extent in order to assure overall bandwidths that are smoothly processible by the system on the assumption of using fixed circuits and fixed applications.
However, when the computer uses the plurality of the circuit blocks of the FPGA and other equivalent programmable logic devices, the arbitration or the allocation of the bandwidths of the bus for connecting the CPU, the memory and other equivalent components to the respective circuit blocks are not adequately conducted as the case may be. For example, as in nowadays, pluralities of applications, threads and virtual machines (users) share the plurality of the accelerators for use, in which case the arbitration or the allocation of the bandwidths might not be adequately carried out. Further, e.g., when processing time of a certain specified accelerator becomes a bottleneck in a certain application, such a circumstance might occur that a priority is desired to be given to this accelerator to the greatest possible degree. However, the processing time of this specified accelerator does not necessarily become the bottleneck to other applications. Accordingly, such a state might occur that bandwidth limitation is set in the specified accelerator in other applications, but it is desirable to give the priority to, rather, other applications. In other words, it might happen that focusing on the specified application is not optimal to the computer system on the whole.